Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension

Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension

Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension

Imperas Software has announced that Andes Technology, a supplier of 32/64-bit RISC-V CPU cores and a member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension.

As a consequence, developers will now be able to use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.

The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements.

The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.

The Imperas simulation technology enables fast and accurate virtual platforms that are essential to modern SoC design and embedded software development. Working with lead customers, the Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.

Optimising a multicore design is challenging with multiple independent processing units interacting with each other plus shared peripherals together with real-time processing tasks supporting a mix of OS/RTOS running firmware and application software.

SoC architecture exploration allows a full evaluation of software running before the final decision and configuration of the hardware options. These virtual prototypes support early software development, often many months before silicon prototypes are available. For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code.

“RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr. Charlie Su, President and CTO at Andes Technology. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”

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