“ UART (Universal Asynchronous Receiver Transmitter) is a widely used short-distance serial transmission interface. Often used in short-distance, low-speed, low-cost communications. Chips such as 8250, 8251, and NS16450 are common UART devices. The basic UART communication only needs two signal lines (RXD, TXD) to complete the mutual communication of data, and the reception and transmission are full-duplex. TXD is the UART sending end, which is the output; RXD is the UART receiving end, which is the input.
UART (Universal Asynchronous Receiver Transmitter) is a widely used short-distance serial transmission interface. Often used in short-distance, low-speed, low-cost communications. Chips such as 8250, 8251, and NS16450 are common UART devices. The basic UART communication only needs two signal lines (RXD, TXD) to complete the mutual communication of data, and the reception and transmission are full-duplex. TXD is the UART sending end, which is the output; RXD is the UART receiving end, which is the input.
The basic features of UART are: (1) There are two states on the signal line, which can be distinguished by logic 1 (high level) and logic 0 (low level). When the transmitter is idle, the data line should be held at a logic high state. (2) Start Bit (Start Bit): The transmitter starts a character transmission by sending the start bit. The start bit makes the data line in a logic 0 state, indicating that the receiver data transmission is about to start.
(3) Data Bits: The data bits are transmitted after the start bit. The data bits are generally 8-bit data of one byte (there are also 6-bit and 7-bit cases), the low-order bit (LSB) is in the front, and the high-order bit (MSB) is in the back. (4) Parity Bit: It can be considered as a special data bit. The parity bit is generally used to judge whether the received data bits are in error or not, which is generally parity check. In use, this bit is often deselected.
(5) Stop bit: The stop bit is at the end to mark the end of a character transmission, which corresponds to the logic 1 state. (6) Bit time: the time width of each bit. The bit widths of the start bit, data bit, and check bit are consistent, and the stop bit has the format of 0.5 bit, 1 bit, and 1.5 bit, generally 1 bit. (7) Frame: The time interval from the start of the start bit to the end of the stop bit is called a frame.
(8) Baud rate: The transmission rate of the UART, which is used to describe the speed of data transmission. In serial communication, data is transmitted in bits, so the transmission rate is represented by the number of data bits transmitted per second, which is called the baud rate. Such as baud rate 9600=9600bps (bits/second).
FPGA UART system composition: As shown in the figure below, FPGA UART consists of three sub-modules: baud rate generator; receiving module; sending module;
Module design: The system consists of four parts: top module; baud rate generator; UART receiver; UART transmitter.
The top-level module of the asynchronous transceiver consists of a baud rate generator, a UART receiver, and a UART transmitter. The purpose of the UART transmitter is to convert the parallel data to be output into the TXD signal serial output according to the basic UART frame format. The UART receiver receives the RXD serial signal and converts it to parallel data.
The baud rate generator is designed to generate a local clock signal much higher than the baud rate to continuously sample the input RXD to keep the receiver and the transmitter in sync. The baud rate generator is actually a frequency divider. The baud rate frequency division factor can be calculated according to the given system clock frequency (crystal oscillator clock) and the required baud rate, and the calculated baud rate frequency division factor is used as the frequency division number of the frequency divider. The baud rate divider factor can be changed according to different application needs.
Since the serial data frame and the receiving clock are asynchronous, the transition from logic 1 to logic 0 can be regarded as the start bit of a data frame. However, in order to avoid the influence of glitches and get the correct start bit signal, it must be required that at least half of the received start bits belong to logic 0 during the sampling process of the baud rate clock before it can be determined that the received start bit is a start bit. bit. Since the internal sampling clock bclk period (generated by the baud rate generator) is 16 times the transmit or receive baud rate clock frequency, the start bit requires at least 8 consecutive bclk periods of logic 0 to be received before it is considered a start bit. bits are received, then the data bits and parity bits will be sampled every 16 bclk cycles (i.e. every baud rate clock). If the start bit is indeed 16 bclk cycles long, then the following data will be sampled at the midpoint of each bit.
The Links: LQ14D311 VBO125-12N07