[Introduction]This article describes the timing factors and solutions involved in maintaining accuracy while reducing power consumption in low-power systems for measurement and monitoring applications. This article analyzes the analog front-end timing, ADC timing, and digital interface timing. This article also presents examples of Analytical Control Evaluation (ACE) timing tools designed to help system designers and software engineers visualize the impact or setup on measurement timing. The first part begins with an overview of the two main types of ADCs, focusing primarily on the sigma-delta architecture. The second section describes considerations related to the SAR ADC architecture.
“Time is of the essence” – this old idiom can be applied to any field, but when applied to the sampling of real-world signals, it is the backbone of our engineering discipline. When trying to reduce power consumption, achieve timing goals, and meet performance requirements, one must consider which ADC architecture type to choose for the measurement signal chain: sigma-delta or successive approximation register (SAR). Once a specific architecture has been selected, the system designer can create the required circuitry to achieve the necessary system performance. At this point, designers need to consider the most important timing factors for their low-power precision signal chain.
Figure 1. Signal Chain Timing Considerations
Need High Speed: SAR or Sigma-Delta for Low-Power Signal Chains?
We will focus on precision low-power measurements and signals (such as temperature, pressure, and flow) with measurement bandwidths below 10 kHz (see Precision Low-Power for more information), but many of the topics covered in this article can also be applied to wider bandwidths measurement system.
In the past, when exploring low-power systems, designers opted for sigma-delta ADCs for higher-accuracy measurements of slow-moving signals. SARs are considered more suitable for high-speed measurements that require converting more channels, but newer SARs such as the AD4630-24 are entering the high-accuracy realm where sigma-delta ADCs have traditionally been used, so the above statement is not a hard and fast rule. For practical examples of ADC architectures, let’s look at two low-power products and consider the timing associated with the ADC signal chain architecture: the AD4130-8 sigma-delta ADC and the AD4696 SAR ADC, as shown in Table 1.
Table 1. Ultra-low-power ADCs
Sampling frequency or output data rate?
The SAR converter samples the input, capturing the signal level at a known point in time. The initial sample (and hold) phase is followed by a conversion phase. The time it takes to get a result depends heavily on the sampling frequency.
The sigma-delta converter samples at the modulator frequency. The modulator oversamples, and the sampling rate is much higher than the Nyquist frequency of the input signal. The extra frequency span allows noise to be shifted to higher frequencies. The ADC then uses a process called “decimation” on the modulator output, which trades down the sampling rate for more accuracy. It is done with a digital low-pass filter, which is equivalent to an averaging operation in the time domain.
Different technologies obtain conversion results in different ways. The concept used in SAR product documentation is the sampling frequency (fSAMPLE), while the data sheets for sigma-delta products use the output data rate (ODR). When discussing these architectures in detail relative to time, we guide the reader to distinguish between the two.
Figure 2. SAR (ƒSAMPLE) vs. Sigma-Delta (ODR)
For a multiplexed ADC that performs one conversion on multiple channels, the time required to perform the conversion on all channels (including settling time, etc.) is called the throughput rate.
The first timing consideration for the signal chain is the time it takes to bias/excite the sensor and power up the signal chain. Voltage and current sources need to be turned on, sensors need to be biased, and start-up time specifications need to be considered. For example, the AD4130-8 on-chip reference has a turn-on settling time of 280 µs for a specific load capacitance on the reference pin. The on-chip bias voltage (which can be used to excite the sensor) has a start-up time of 3.7 µs per nF, but this depends on the capacitance connected to the analog input pins.
After examining the power-up time in the signal chain, we need to understand the timing considerations associated with the ADC architecture. In the next part of this article, we will first focus on the measurement signal chain centered on sigma-delta ADCs in ultra-low power applications, and the important timing considerations associated with such ADCs. The SAR and sigma-delta signal chains have some overlap in terms of impacting timing, such as using techniques to minimize microcontroller interaction time, enabling system-level power improvements. These will be highlighted in the subsequent discussion of the SAR ADC signal chain.
Signal Chain Timing Considerations When Using Sigma-Delta ADCs
If the ADC of choice is a sigma-delta type rather than a SAR type, there is a specific set of timing factors to consider. When looking at the signal chain, the main areas to explore are the analog front-end timing, ADC timing, and digital interface timing, as shown in Figure 1.
Analog Front End Timing Considerations
We’ll explore these three modules separately, starting with the Analog Front End (AFE). AFEs can vary by design type, but there are some common aspects that apply to most circuits.
Figure 3. AFE Sigma-Delta Timing Considerations
The AD4130-8, part of the Precision Low Power Signal Chain product group, has been designed with a rich feature set to achieve high performance while reducing power consumption. Some of these features include on-chip FIFO, smart channel timing controller and duty cycle control.
The AD4130-8 is an ultra-low power sigma-delta ADC from Analog Devices. Considering that it contains many key signal chain building blocks on-chip, such as on-chip voltage references, programmable gain amplifiers (PGAs), multiplexers, sensor excitation current or sensor bias voltages, the ultra-low current is impressive .
The device’s AFE includes an on-chip PGA that minimizes analog input current, eliminating the need for an external amplifier to drive the input. The digital filter after oversampling ensures that the bandwidth is mainly controlled by the digital filter. The AD4130-8 provides multiple on-chip sinc3 and sinc4 filters, plus additional filters for 50 Hz and 60 Hz noise rejection. The sinc3 and sinc4 digital filters require an external anti-aliasing filter as a complement. The effect of this anti-aliasing filter is to limit the amount of bandwidth of the input signal. This is to ensure that noise (such as the rate of change of the modulator frequency fMODnoise) will not alias into the passband and conversion results.
Figure 4. AD4130 Sigma-Delta Simplified System module
Figure 5. Simulation of combined external and internal filtering
Higher-order anti-aliasing filters can be used, but a first-order, single-pole, low-pass filter is usually sufficient. The filter is designed based on sampling the target signal, and Equation 1 determines the 3 dB bandwidth of the filter:
When choosing capacitor and resistor values, higher resistor values are preferable but may increase noise, while lower capacitor values have a limit after which the ratio of pin capacitance to external capacitance becomes a relevant factor .
It is important to determine how long it takes for the circuit to charge based on the largest voltage step that can be seen on this capacitor.
Figure 6. First-Order Low-Pass Anti-Aliasing Filter
The voltage across the capacitor will change over time with a rate of change
VC = the voltage across the capacitor at a point in time
t = time
Figure 7. First-Order Low-Pass Filter Settling Time in Response to 1 V Full-Scale Step Change
On power-up, the step size VSmay be equal to the entire input voltage range of the ADC (±VREF/gain).
Figure 7 shows that after 4 time constants ( = R × C), the signal has reached 0.98 × VS. The required number of time constants can be calculated by calculating the step size VSto obtain the natural logarithm of the ratio.
NTis the number of time constants to wait during which the input settles to half of 1 LSB of the ADC input voltage range (VHALF_LSB) within. V in the above formulaHALF_LSBAn appropriate value can be substituted according to the required voltage accuracy. If the system designer wanted the resolution to be within half an LSB, for a bipolar input ADC with N-bit resolution and an internal PGA gain of 1, this would be:
The time t required to get the actual input voltageACQis equal to the number of time constants multiplied by,is equal to RC:
Traditionally, when switching between channels of a multiplexed ADC, large voltage swings between channels (one channel at negative full scale, the next at positive full scale) would require similar calculations. The AD4130-8 solves this problem by implementing a low-power on-chip precharge buffer that turns on when switching channels. This ensures that the first conversion after switching channels will work correctly at the fastest data rates. The device also has an on-chip PGA designed to achieve the full common-mode input range, which provides system designers with more headroom to handle a wider range of common-mode voltages. This is useful for measuring signals, but in the worst case, one channel may be at negative full scale and the next channel may be at positive full scale.
Figure 8. Isolated AD4130-8 Circuit with Low-Pass Filter
Example: Analog Front-End Low-Pass Filter
The example in Figure 8 shows a Wheatstone bridge sensor with –3 dB filtering for a 24-bit ADC below 16 kHz.
R = 1 kΩ, C = 0.01 µF, VREF = 2.5 V, PGA gain set to 1:
The single-ended filter in Figure 8 shows the primary sensor R = 1 kΩ and C = 0.01 µF:
The differential signal filter in Figure 8 shows the primary sensor R = 1 kΩ and C = 0.1 µF. See MT-070 for more information on the formula:
The differential sensor time constant dominates the single-ended value, so it will determine the calculation of the overall system:
This is the amount of time the system designer needs to allow the filter to settle externally at power-up before collecting samples. This can be done in the digital domain by dropping samples, or the sampling instant can be delayed to account for charging.
When designing a filter, the resistor and capacitor values may differ from those shown earlier. System designers can use LTspice® to model filters with the AD4130-8. LTspice can also be used to model a system or signal chain, as shown in Figure 9: Simulating RTD behavior by changing R2.
Figure 9. RTD (R2) circuit simulation in LTspice
ADC Timing Considerations
Recalling the relationship between output data rate and sigma-delta ADC timing, let’s now discuss the internal timing associated with this type of ADC.
Figure 10. Sigma-Delta ADC Timing Considerations
Such converters use a low-resolution (1-bit) ADC to digitize analog signals at high sampling rates. Using oversampling techniques in conjunction with noise shaping and digital filtering can increase the effective resolution.
By writing to the digital registers via the SPI interface, the user can control the oversampling and decimation rates of the AD4130-8. Modulator sample rate (fMOD)It is fixed. The FS value essentially changes the number of samples (in increments of 16 for the AD4130-8) the digital filter uses to arrive at the result. Changing the FS word changes the number of oversampling modulation clock cycles for each ADC result.
Figure 11. Extraction
Decimation reduces the effective sampling rate of the ADC output, allowing for greater accuracy. Decimation can be viewed as a method to remove redundant signal information introduced by the oversampling process. The more decimation used (the more samples included in the digital filter calculation), the more accurate the digital filter can achieve, but the slower the output data rate will be.
fADC for the output data rate
fMOD master clock frequency
FS is the multiplier used to control the decimation rate
When multiple channels are enabled, the data sheet output data rate or ODR (fADC) and data throughput rates are more complex. This is because there is a delay in the digital filter when switching channels. The time required for the digital filter to settle depends on the sinc filter type. Figure 12 shows that the first conversion of the sinc3 filter requires three conversion cycles until the digital equivalent of the analog input is reached. The first conversion of the sinc4 filter requires four conversion cycles. tSETTLEis the user-programmable settling time to account for multiplexer switching. The higher the filter order, the lower the noise, but the disadvantage is that it will take more conversion cycles for the filter to settle.
Figure 12. Filter Delay
Digital Interface Timing Considerations
To help understand the digital interface timing of a sigma-delta ADC such as the AD4130, the ADI software tool ACE provides a model. Timing tools are part of several software tools integrated into the ACE software. We can help understand these configurations with the timing controller timing diagram and FIFO timing diagram.
Figure 13. AFE Sigma-Delta Digital Interface Timing Considerations
The AD4130-8 timing controller allows different input channels to have different digital filter and settling configurations and timings. Time series tools simplify the calculation of when data is ready to be read.
When multiple channels are enabled, the user should not mistakenly read the established channel ODR and divide by the number of enabled channels to calculate the throughput rate, as this does not account for digital filter delays. The filter delay should be considered when calculating the throughput rate (effective ODR vs data sheet ODR). When multiple channels are enabled, the initial setup time (tSETTLE) and the number of internal conversion cycles (t1st_CONV_IDEAL), as shown in Figure 14.
Figure 14. Output Data Rate of First Conversion Including Filter Delay
If all channels have the same filter and settling configuration, and there are no duplicate conversions on any channel, the throughput rate of the system is:
CHs = number of enabled channels
t1ST_CNV_IDEAL = transition time including filter delay
tSETTLE = digitally controlled timing parameters, can be extended, but has a minimum programmable time to allow for multiplexer settling
The throughput rate can be calculated by summing the 1CNV_ODR time, which is the time between the green squares in Figure 14.
Example: Pressure Sensor Signal Chain Timing
Figure 15. Simplified Pressure Sensor System Block Diagram
Suppose you want to design a system with multiple pressure sensors (represented by the pressure sensor in Figure 15), accompanied by a temperature sensor:
Question A: How many pressure sensors can be deployed in the system relative to each AD4130-8?
Question B: If the pressure sensor has a voltage output range of 3 mV/V, what is the expected resolution?
Question C: If a production line in a factory requires at least 14 bits of effective resolution to meet the dynamic range requirements of the system, how many load cells does the system consist of?
Step 1: Choose Gain
AVDD = 1.8V. REFIN+ to REFIN– = 1.8 V
A 1.8 V excitation for a 3 mV/V load cell will result in a maximum output of 5.4 mV per load cell.
Maximum gain of PGA = 128.
The voltage at the ADC input is 5.4 mV × 128 = 0.7 V, which is well within the 1.8 V range. A PGA gain of 128 is the correct gain to use.
Step 2: Choose the FS value
We want to choose the fastest setting supported by a sinc3 filter and FS=1.
Figure 16. Calculating t using the Timing Tool1CNV_ODRSum
Step 3: Use the throughput rate of one channel to calculate the number of channels in the system
1CNV_ODR = (1/1.667 ms) 600 SPS.
Throughput rate = 600 SPS/Nch.
1CNV_ODR = throughput rate of a single channel in a multi-channel system with the same configuration and no duplicate conversions.
10 channels can be sampled at a sampling rate of 60 SPS.
Answer A: Each system has nine load cells.
Step 4: Use the Effective Resolutions table from the datasheet
Also note that when looking at the noise and effective resolution table, the calculations are based on the FS filter value, not the throughput rate. The ODRs listed here are the ODRs for a single established channel.
Figure 17. FS Word vs Gain
System designers need to be careful when interpreting data sheets. The throughput rate (in SPS) is reduced when multiple channels are enabled. It is important to note that readers may misinterpret the resolution table in the data sheet, thinking that higher resolutions can be achieved. For ODR of established channels, to achieve higher accuracy, changes in FS cause increased oversampling and decimation, which slows down the system. With multiple channels enabled, the slowdown in reading each ADC channel (SPS, or throughput rate) is due to sampling multiple channels, not an increase in oversampling. Therefore, the resolution does not increase.
Figure 18. Data Sheet Table of Resolution vs Gain
If we look at the table in the datasheet, we see that for FS = 1 and gain = 128, the effective resolution is 11.7 bits.
Answer B: 11.7 bits.
In order to solve C, we need to go back a few steps in part A:
Step 2: Choose the FS value
This time, we choose the FS value according to the resolution requirement. To achieve an effective resolution of 14 bits, FS = 3 should be chosen.
Step 3: Use the throughput rate of one channel to calculate the number of channels in the system
Figure 19. Use timing tool to change filter type and FS value and read output data rate of first conversion including filter delay.
We can use sequential AFM to achieve the desired resolution (1/4.167 μs).
240 SPS/Nch = throughput rate.
At this data rate, we can use four channels.
Answer C: Three channels.
Duty cycle control
Some systems have lower throughput rates and higher output data rates, such as health monitoring devices, where the host controller puts the system in standby mode most of the time, switching only periodically. The AD4130-8 provides duty cycle control, the user can convert continuously, the device enters standby mode with a duty cycle of 3/4 or 15/16, and converts with a duty cycle of 1/4 or 1/16. Active and standby times are related to user-selected settings.
Figure 20. Duty Cycle Control
The AD4130-8 also has a SYNC pin that allows the user to deterministically control when a conversion occurs on a preselected number of channels. The device can also be configured to operate in low-current standby mode, initiate a conversion sequence, leave the low-current state, perform conversions on multiple channels, and return to standby mode when conversions are complete.
Example: Enabling Duty Cycle Control
Using the same settings as the previous pressure sensor signal chain example, throughput rate = 600 SPS/Nch, with both channels enabled, the ODR becomes 300 SPS, and with a 3 V supply, the average current will be 28.7 µA (see Figure 21 ).
Figure 21. Throughput Time and Current Before Duty Cycle Control Enabled
With a duty cycle of 1/16 enabled, the throughput rate becomes 24.489 SPS, while the average current during the period becomes 4.088 µA (40.834 ms; see Figure 22).
Figure 22. Throughput Time and Current with Duty Cycle Control Enabled
The AD4130-8 includes an on-chip FIFO. The FIFO can buffer conversion results, giving the microcontroller or host controller the opportunity to enter a low-power state while waiting for a conversion, thereby reducing system power consumption. The biggest timing consideration here is to ensure that the host reads back the FIFO fast enough to avoid missing conversions while converting continuously.
The user can periodically read the FIFO when a specified number of samples (also known as watermarks) have been collected. When the desired number of samples is reached, an interrupt is available and the host reads back the FIFO. The FIFO needs to be emptied to clear the interrupt. The user has a predefined time period to read back data from the FIFO. The SCLK frequency used will determine how much data the user can read without missing a transition.
Through the ACE software timing tool, users can change the SCLK frequency while designing the system, or use gated clocks to inform the user when the watermark level needs to be reduced. For example, FIFO readback.
Taking a continuous single channel measurement with a maximum ODR of 2400 kSPS as an example, if the watermark level is set to 256 and we try to read back, we have 729.2 µs to read back the FIFO without missing any transitions. The user needs to read back 4112 bits. The tool informs the user that in order to read back the FIFO and not miss conversions, the host SPI clock frequency must be 5.64 MHz. This exceeds the device’s maximum specification of 5 MHz, an error occurs, and the user can modify the watermark to avoid deviating from the specification.
Figure 23. AD4130-8 ACE Software FIFO Readback Window and Alerts
Table 3. Sigma-Delta Summary
When using sigma-delta ADCs, we can see that there are many tradeoffs, timing factors, and characteristics to consider. The second part of this article will examine SAR ADC technology, and the factors and characteristics that affect timing in a SAR ADC system.
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